As is known, the SDH standard prescribes pre-established transmission velocities: 51.84 Mbit/sec. (base velocity), 155.52 Mbit/sec., 622.08 Mbit/sec. etc. The prescribed transmission velocities are all whole multiples of the base velocity.
Within the scope of the SDH standard, recommendation G.703 issued by the CCITT committee of the International Telecommunication Union (ITU) prescribes the electro-physical characteristics of the hierarchical digital interfaces to be used for interconnecting components of digital networks which conform to the SDH standard. In particular, recommendation G.703 prescribes the type of coding of the data to be used for each transmission velocity: for example, for the transmission/reception interfaces (also termed bidirectional interfaces or “transceivers”) at 155.52 Mbit/sec. the CMI coding should be used. The CMI coding is a code with two levels, A1 and A2, in which a binary “0” is coded so as to present the two levels A1 and A2 in succession, each for a time equal to half the bit time, while a binary “1” is coded by means of one or other of the two levels A1 or A2 maintained for the whole bit time; the two levels A1, A2 are alternated with each other for successive binary “1”s.
The interface is generally associated with digital circuits for processing the data received and/or to be transmitted, which typically operate on differently coded data, for example according to the NRZ (Non-Return to Zero) coding. In reception, the interface should therefore receive, from a remote analogous interface through a transmission/reception channel consisting, for example, of a pair of coaxial cables, a signal carrying CMI-coded data, recognize them and convert them into NRZ, and deliver them to the digital circuits which are to process them. In transmission, the interface should receive from the digital processing circuits NRZ-coded data, recognize them and convert them into CMI, and pass them to the transmission/reception channel.
It being a matter of synchronous data transmission, the question of timing is of maximum importance.
In transmission, it is necessary to have available a clock signal having a period equal to half the bit time. Since a high precision and a low “jitter” must be guaranteed, use is normally made of a local oscillator in a phase locked loop (PLL for short).
In reception, the CMI-coded signal is processed in order to extract, or recover, a clock signal (strobe), necessary for synchronizing the interface with the flow of data received, which is then used to recognize the bits of data and NRZ-code them.
There are three known techniques for the recovery of the clock signal in reception (RX clock recovery) by the interfaces. A first technique makes use of an analog PLL which tracks a signal having double the frequency with respect to the frequency of the bits of data. In a second technique, a resonator tuned to twice the bit frequency is used. In a third technique, use is made of quadri-correlator circuits. In all cases, it is necessary to start from a local clock signal, different from that used for transmission. In the interface there are therefore two separate time bases, one for transmission and one for reception.
The use of two separate time bases, one for transmission and the other for reception, has drawbacks from various points of view. Apart from the obvious problem of increase in the circuit area, in the cost in terms of components, and in power consumption, there are problems of interference (cross-talk) between the two clock signals, having a very similar frequency to each other, which can give rise to beating, with a negative effect on performances.